Many attempts have been made in the prior art to protect semiconductor devices, including biopolar transistors, field effect devices, and integrated circuits against damage due to voltage and current transients. A particular problem with field effect devices has been their protection from electrostatic discharge (ESD).
Fischer, U.S. Pat. No. 3,787,717, teaches the use of a lateral bipolar transistor for protecting a field effect device. The lateral bipolar transistor includes a gated collector junction, and has its collector-to-emitter current path shunting the point in the circuit to be protected against overvoltage. Metallization is placed over a silicon dioxide passivation layer covering the collector junction, and electrically connected to the point in the substrate to be protected. Similarly the emitter electrode is connected to the point to be protected. When an over voltage occurs, the gated collector junction breaks down in an avalanche mode, allowing current to flow therefrom to the substrate, causing a potential drop in the base region of the lateral transistor, in turn causing the latter to conduct for shunting away excess current due to the overvoltage condition.
Hartranft et al., U.S. Pat. No. 4,605,980, teaches the use of a thick field effect transistor in combination with a thin field effect transistor to protect an integrated circuit, more specifically, to protect a field effect transistor from damage due to excessively high voltages and currents generated by electrostatic discharge. The protection circuit is formed on the same substrate and includes the a field effect transistor to be protected. A resistor-diode network is included in the circuitry for the thick field effect transistor. An elongated diffused resistor is included between an integrated circuit pad and the circuit to be protected. The thick field effect transistor is used to shunt high voltages and currents generated by electrostatic discharge away from the protected device, whereas the thin field effect transistor is used to protect against lower but still excessive voltages relative to the device being protected. There is no interaction between the thin and thick field effect transistors, other than each being employed for protecting a device over different ranges of voltage and current.
Rountree et al., U.S. Pat. No. 4,692,781, teaches an input protection circuit for a field effect transistor using a thick oxide transistor for providing the main protection to the device. The thick oxide field effect device serves to protect the integrated circuit against relatively high voltages. A thin gate field effect transistor is used to provide low voltage protection, and serves as a "field plate diode".
Hartranft et al., U.S. Pat. No. 4,745,450, teaches a circuit for protecting a thin gate oxide field effect transistor from puncture due to electrostatic discharge. The teachings of this invention are substantially similar to those of U.S. Pat. No. 4,605,980.
Puar, U.S. Pat. No. 4,786,956, discloses a device for protecting an integrated circuit from high input voltages, wherein the integrated circuit includes a semiconductor substrate with a recessed field-oxide region laterally separating active semiconductor portions. The protection device includes an N channel enhancement-mode field effect device having a source for receiving a first voltage, an insulated-gate electrode, and a drain electrode coupled to an input terminal, with the source and drain regions lying in one of the active portions along the upper surface of the substrate. A resistor is included for coupling the second voltage through the gate of the NMOS transistor. Another NMOS transistor, more specifically a thick-oxide device, has a source region lying in one of the active portions along the upper surface of the substrate coupled to the source of the first NMOS transistor, a gate electrode coupled to the input signal terminal, and a drain region lying in another of the active portions of the substrate along the upper surface thereof, that is also coupled to the input terminal.
Maloney, U.S. Pat. No. 4,821,096, discloses a device for protecting a semiconductor device from voltage and current surges, such as caused by electrostatic discharge. The protection device or circuit includes a first PNP lateral transistor having an emitter region coupled to an input terminal of the device, a base region also connected to the input terminal, and a collector region coupled to ground. Further included is a second PNP lateral transistor having an emitter region coupled through a resistor to the input terminal, and base and collector regions coupled to ground. The protection device serves to shunt high voltage surges and current spikes to ground, away from the device being protected. Another embodiment of the invention includes a pair of P.sup.- type field effect transistors in a similar configuration, for protecting a semiconductor device.
Duvvury et al., U.S. Pat. No. 4,855,620, teaches the inclusion of a high threshold voltage field effect transistor for the active output transistor of a field effect transistor output buffer circuit. The high threshold voltage field effect device has its source-to-drain path connected between the power supply and the gate electrode of the output transistor. The high threshold voltage field effective device also has its gate connected to the output terminal of the output terminal. If an ESD transient occurs at the output terminal, the high threshold field effect device will conduct to protect the field effect transistor output buffer circuit, in that the former has a threshold voltage that is greater than the operating voltage of the output buffer, but less than the collector-base junction breakdown voltage to a parasitic bipolar transistor located in the output of the buffer circuit.
As very large scale integrated (VLSI) circuit geometries have continued to shrink, the decrease in the corresponding gate oxide thickness, relative to breakdown voltage, has been greater than the decrease in reverse junction breakdown of the typically available diffusions used to protect the oxide. At the one micrometer level, the difference in breakdown voltage is only a few volts. Also, the initial breakdown voltage of one of the commonly used structures, a thick oxide NMOS transistor snap-back device, is too high to provide protection for the related integrated circuit. Known protection circuits and devices are unable to meet the protection requirements for state-of-art VLSI devices.